Forum Discussion
Altera_Forum
Honored Contributor
16 years agoWhen I use the "set_max_skew" like shown above I get:
--- Quote Start --- Warning: No path is found satisfying assignment "set_max_skew -from [get_clocks {clk_epcs}] -to [get_ports {*ALTERA_DCLK}] 1.000 ". This assignment will be ignored. --- Quote End --- When I remove the "set_max_skew" line I get: --- Quote Start --- Unconstrained Output Port: asmi_slave:asmi_inst|asmi:asmi_inst|asmi_altasmi_parallel_t852:asmi_altasmi_parallel_t852_component|cycloneii_asmiblock3~ALTERA_DCLK No output delay, min/max delays, false-path exceptions, or max skew assignments found. This port has clock assignment. Unconstrained Output Port Paths: pll|altpll_component|auto_generated|pll1|clk[1] No output delay, min/max delays, false-path exceptions, or max skew assignments found. This port has clock assignment. --- Quote End --- So how do I fix it ? Is it a bug in Quartus ?