TimeQuest .sdc constraints for EPCS (ALTASMI_PARALLEL megafunction)

No, that is the problem. It seams they do not work with it but also do not work without it.

I filed a service request with altera, let's see what they say about it.

--- Quote Start ---

ngcreese, you are correct. I had a copy paste error in the forum, (I corrected it now) but the .sdc file that I used with TimeQuest was correct. So Your tip did not help me.

--- Quote End ---

No worries man. Glad your constraints are working for you without this skew constraint.

There seems to be two different clocks in these statements:

# EPCS clk output

create_generated_clock -name {epcs_dclk} -source [get_pins {pll|altpll_component|auto_generated|pll1|clk[1]}] [get_ports {*ALTERA_DCLK}]

set_max_skew -from [get_clocks {clk_epcs}] -to [get_ports {*ALTERA_DCLK}] 1

Was that intended?

I would think you might have ment something more like this:

# EPCS clk output

create_generated_clock -name {clk_epcs} -source [get_pins {pll|altpll_component|auto_generated|pll1|clk[1]}] [get_ports {*ALTERA_DCLK}]

set_max_skew -from [get_clocks {clk_epcs}] -to [get_ports {*ALTERA_DCLK}] 1

In order for the "set_max_skew" command to be applied to the design by the tools.

When I use the "set_max_skew" like shown above I get:

--- Quote Start ---

Warning: No path is found satisfying assignment "set_max_skew -from [get_clocks {clk_epcs}] -to [get_ports {*ALTERA_DCLK}] 1.000 ". This assignment will be ignored.

--- Quote End ---

When I remove the "set_max_skew" line I get:

--- Quote Start ---

Unconstrained Output Port:

asmi_slave:asmi_inst|asmi:asmi_inst|asmi_altasmi_parallel_t852:asmi_altasmi_parallel_t852_component|cycloneii_asmiblock3~ALTERA_DCLK

No output delay, min/max delays, false-path exceptions, or max skew assignments found. This port has clock assignment.

Unconstrained Output Port Paths:

pll|altpll_component|auto_generated|pll1|clk[1]

No output delay, min/max delays, false-path exceptions, or max skew assignments found. This port has clock assignment.

--- Quote End ---

So how do I fix it ? Is it a bug in Quartus ?

Here is what I got so far:

--- Quote Start ---

# Create external XTAL Clock input

create_clock -name {CLK_50MHZ_PLL[4]} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLK_50MHZ_PLL[4]}]

# Create PLL Generated Clocks 100MHz and 25MHz

create_generated_clock -name {clk} -source [get_pins {pll|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 2 -master_clock {CLK_50MHZ_PLL[4]} [get_pins {pll|altpll_component|auto_generated|pll1|clk[0]}]

create_generated_clock -name {clk_asmi} -source [get_pins {pll|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 1 -divide_by 2 -master_clock {CLK_50MHZ_PLL[4]} [get_pins {pll|altpll_component|auto_generated|pll1|clk[1]}]

# Constrain the *ALTERA_DCLK output port from the ALTASMI_PARALLEL megafunction

set_min_delay -from [get_pins {pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_ports {*ALTERA_DCLK}] 5.1

set_max_delay -from [get_pins {pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_ports {*ALTERA_DCLK}] 7.1

# EPCS clk (virtual clock at the input pin of the EPCS device)

create_generated_clock -name {clk_epcs} -source [get_pins {pll|altpll_component|auto_generated|pll1|clk[1]}] [get_ports {*ALTERA_DCLK}]

set_max_skew -from [get_clocks {clk_epcs}] -to [get_ports {*ALTERA_DCLK}] 0.2

# Set Clock Uncertainty

derive_clock_uncertainty

# Board trace delays

set max_btd 0.2

set min_btd 0.1

# Set Input Delay, see Table 3-17 of the EPCS Datasheet# **************************************************************

set_input_delay -max [expr $max_btd +8 +$max_btd] -clock { epcs_dclk } -clock_fall [get_ports {*ALTERA_DATA0}]

set_input_delay -min [expr $min_btd +5 +$min_btd] -clock { epcs_dclk } -clock_fall [get_ports {*ALTERA_DATA0}]

# Set Output Delay, see Table 3-16 of the EPCS Datasheet# **************************************************************# Do not violate tSLCH (t ce setup)

set_output_delay -add_delay -max -clock [get_clocks {clk_epcs}] [expr +$max_btd +10 -$min_btd] [get_ports {*ALTERA_SCE}]# Do not violate tCHSL (t ce hold)

set_output_delay -add_delay -min -clock [get_clocks {clk_epcs}] -[expr +$min_btd +10 -$max_btd] [get_ports {*ALTERA_SCE}]

# Do not violate tDVCH (t data setup)

set_output_delay -add_delay -max -clock [get_clocks {clk_epcs}] [expr +$max_btd +5 -$min_btd] [get_ports {*ALTERA_SDO}]# Do not violate tCHDX (t data hold)

set_output_delay -add_delay -min -clock [get_clocks {clk_epcs}] -[expr +$min_btd +5 -$max_btd] [get_ports {*ALTERA_SDO}]

--- Quote End ---