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Cliver1's avatar
Cliver1
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2 years ago
Solved

TimeQuest report timing finds 2 paths inside the Cyclone 2 FPGA for the same design path

Hello, when I analyse the path from P1_EnergyMonAInClk40m[6] to P1_PeakPowerClk40m[6] for example in my design using Report Timing in TimeQuest 2 paths are reported with different timing delays. The ...
  • Cliver1's avatar
    2 years ago

    False alarm. There are 2 possible data paths in my design!