Forum Discussion
Honored ContributorTime delay
Hello
I want to create time delay using logic gates (not flip-flops) When I put carry gates, or any other gates, the time analyzer shows 0 delay Can anyone help I can use only max-plus (version 10.2)9 Replies
Altera_Forumok thank you
- Altera_Forum
I said, I don't know if it works in MaxPlus. In Quartus, follow the method reported in the said post, using a keep attribute for the respective signals and setting Ignore LCELL Buffers to off. The delay will be shown in simulation, also the compilation report indicates the additional macro cell usage.
- Altera_Forum
so, you say that there no way to see delay from logic elements in maxplus?
what about quartus, do the simulation shows the delay? - Altera_Forum--- Quote Start --- Have you used the keep attributes (outlined above) to stop it doing this? --- Quote End --- Do you know, if these synthesis attrubutes are working with MaxPlus? In addition, it's known that the CPLD synthesizer works partly different from FPGA. With Quartus, additional settings are required for CPLD: http://www.alteraforum.com/forum/showthread.php?t=22110
- Altera_Forum
Im guessing the synthesisor removed your logic as it was seen as redundant. Have you used the keep attributes (outlined above) to stop it doing this?
- Altera_Forum
thank you for response
my work is based on time difference between delay of carry gate and flip-flop I use devise EPM7160ELC84-12 and when i program it, the timing simulator shows 0 delay between the gates unfortunately i cant post images... do anyone knows why is it happening, and what should i do? - Altera_Forum
A useful answer, I hope:
You can apply a 'keep' setting to restrain the compiler from optimizing it away. In VHDL:
There is similar setting in Verilog. It is 'stuffed' into a comment in the declaration, before the closing semi-colon.signal wire_to_keep : std_logic; attribute keep: boolean; attribute keep of wire_to_keep: signal is true;
AHDL is very Spartan (no pun intended):wire keep_wire /* synthesis keep */;output = LCELL( input ) ; - Altera_Forum
Cascading logic cannot create a guaranteed time delay because the routing can vary. Never rely on it to create a specific time delay.
The only way to create a reliable time delay is with flip-flops. - Altera_Forum
I guess you want to cascade 'AND' gates :-) (70's technology inside ;-))
I think it is optimized at the synthesis task : it is just simplified by using a simple interconnection. Maybe use a delayed clock. I am not sure it is a good idea.
