Time delay

A useful answer, I hope:

You can apply a 'keep' setting to restrain the compiler from optimizing it away.

In VHDL:

signal wire_to_keep : std_logic;  
attribute keep: boolean; 
attribute keep of wire_to_keep: signal is true; 

There is similar setting in Verilog. It is 'stuffed' into a comment in the declaration, before the closing semi-colon.

wire keep_wire /* synthesis keep */; 

AHDL is very Spartan (no pun intended):

 output = LCELL( input ) ;