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Altera_Forum
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15 years ago

Time delay

Hello I want to create time delay using logic gates (not flip-flops) When I put carry gates, or any other gates, the time analyzer shows 0 delay Can anyone help I can...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I said, I don't know if it works in MaxPlus. In Quartus, follow the method reported in the said post, using a keep attribute for the respective signals and setting Ignore LCELL Buffers to off. The delay will be shown in simulation, also the compilation report indicates the additional macro cell usage.