Hi Donald,
Here is my challenge. Now it is an array of 16 counters each with a synchronous reset.
This is the AHDL code:
SUBDESIGN counts
(
clk : Input;
rst[15..0] : Input;
cnt[15..0][7..0] : Output;
)
VARAIBLE
myCnt[15..0] : LPM_COUNTER WITH (LPM_WIDTH=8, LPM_DIRECTION = "UP");
BEGIN
myCnt[].clock = clk;
myCnt[].sclr = rst[];
cnt[][] = myCnt[].q[];
END;
SpinalHDL
class counters () extends Component {
val rst = in Bits (16 bits)
val cnt = out Vec (Reg(UInt (8 bits)), 16)
for (i <- 0 to 15) {
when (rst(i)){
cnt(i) := 0
} otherwise {
cnt(i) := cnt(i)+1
}
}
}
Do you want to reconsider your views on AHDL "it is very inefficient in terms of time and manpower requirements."
I do not code much in Verilog, but this is the Verilog code generated by SpinalHdl. I hope it can be a better and human readable. I await your comments.
// Generator : SpinalHDL v1.6.4 git head : 598c18959149eb18e5eee5b0aa3eef01ecaa41a1
// Component : counters
`timescale 1ns/1ps
module counters (
input [15:0] rst,
output reg [7:0] cnt_0,
output reg [7:0] cnt_1,
output reg [7:0] cnt_2,
output reg [7:0] cnt_3,
output reg [7:0] cnt_4,
output reg [7:0] cnt_5,
output reg [7:0] cnt_6,
output reg [7:0] cnt_7,
output reg [7:0] cnt_8,
output reg [7:0] cnt_9,
output reg [7:0] cnt_10,
output reg [7:0] cnt_11,
output reg [7:0] cnt_12,
output reg [7:0] cnt_13,
output reg [7:0] cnt_14,
output reg [7:0] cnt_15,
input clk,
input reset
);
wire N1_l20;
wire N1_l20_1;
wire N1_l20_2;
wire N1_l20_3;
wire N1_l20_4;
wire N1_l20_5;
wire N1_l20_6;
wire N1_l20_7;
wire N1_l20_8;
wire N1_l20_9;
wire N1_l20_10;
wire N1_l20_11;
wire N1_l20_12;
wire N1_l20_13;
wire N1_l20_14;
wire N1_l20_15;
assign N1_l20 = rst[0];
assign N1_l20_1 = rst[1];
assign N1_l20_2 = rst[2];
assign N1_l20_3 = rst[3];
assign N1_l20_4 = rst[4];
assign N1_l20_5 = rst[5];
assign N1_l20_6 = rst[6];
assign N1_l20_7 = rst[7];
assign N1_l20_8 = rst[8];
assign N1_l20_9 = rst[9];
assign N1_l20_10 = rst[10];
assign N1_l20_11 = rst[11];
assign N1_l20_12 = rst[12];
assign N1_l20_13 = rst[13];
assign N1_l20_14 = rst[14];
assign N1_l20_15 = rst[15];
always @(posedge clk) begin
if(N1_l20) begin
cnt_0 <= 8'h0;
end else begin
cnt_0 <= (cnt_0 + 8'h01);
end
if(N1_l20_1) begin
cnt_1 <= 8'h0;
end else begin
cnt_1 <= (cnt_1 + 8'h01);
end
if(N1_l20_2) begin
cnt_2 <= 8'h0;
end else begin
cnt_2 <= (cnt_2 + 8'h01);
end
if(N1_l20_3) begin
cnt_3 <= 8'h0;
end else begin
cnt_3 <= (cnt_3 + 8'h01);
end
if(N1_l20_4) begin
cnt_4 <= 8'h0;
end else begin
cnt_4 <= (cnt_4 + 8'h01);
end
if(N1_l20_5) begin
cnt_5 <= 8'h0;
end else begin
cnt_5 <= (cnt_5 + 8'h01);
end
if(N1_l20_6) begin
cnt_6 <= 8'h0;
end else begin
cnt_6 <= (cnt_6 + 8'h01);
end
if(N1_l20_7) begin
cnt_7 <= 8'h0;
end else begin
cnt_7 <= (cnt_7 + 8'h01);
end
if(N1_l20_8) begin
cnt_8 <= 8'h0;
end else begin
cnt_8 <= (cnt_8 + 8'h01);
end
if(N1_l20_9) begin
cnt_9 <= 8'h0;
end else begin
cnt_9 <= (cnt_9 + 8'h01);
end
if(N1_l20_10) begin
cnt_10 <= 8'h0;
end else begin
cnt_10 <= (cnt_10 + 8'h01);
end
if(N1_l20_11) begin
cnt_11 <= 8'h0;
end else begin
cnt_11 <= (cnt_11 + 8'h01);
end
if(N1_l20_12) begin
cnt_12 <= 8'h0;
end else begin
cnt_12 <= (cnt_12 + 8'h01);
end
if(N1_l20_13) begin
cnt_13 <= 8'h0;
end else begin
cnt_13 <= (cnt_13 + 8'h01);
end
if(N1_l20_14) begin
cnt_14 <= 8'h0;
end else begin
cnt_14 <= (cnt_14 + 8'h01);
end
if(N1_l20_15) begin
cnt_15 <= 8'h0;
end else begin
cnt_15 <= (cnt_15 + 8'h01);
end
end
endmodule
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