Forum Discussion

raviganesh's avatar
raviganesh
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

The future for AHDL

AHDL is wonderful language. I have worked on 4 HDL languages, ABEL, AHDL, Verilog and currenlty SpinalHdl. Here is my recent work with SpinalHdl On some aspects like an array of modules, AHDL o...
ak6dn's avatar
ak6dn
Icon for Regular Contributor rankRegular Contributor
4 years ago

Well, to array a construct in systemverilog i would use the generate block construct, so ...

module count (input wire clk, input wire rst, output reg [15:0] cnt [7:0])
genvar i;
generate
    for (i = 0, i < 16; i++) begin
        always @(posedge clk)
            cnt[i] <= rst ? 0 : cnt[i]+1;
    end
endgenerate

So I am done here. You are beating the proverbial dead horse. AHDL is dead. It is not coming back. No one except you wants it.