Occasional Contributor
Occasional ContributorHi Donald,
I immensely appreciate your response and I feel very honored about your reference to my 11 year old post.
Here is my comparison of the verbosities:
Verilog: assign Data = nCE? 16'hffff : 16'h0);
SpinalHdl: Data.setAllTo (nCE)
AHDL: Data[] = nCE
Isn't AHDL short and sweet.
I will come up with another example using an array of modules. Verilog sucks. SpinalHdl pant's. AHDL shines.
I disagree AHDL is only for low level. Its state machines are as as good as SpinalHdl and far better than Verilog. It has tables and there is no equivalent in Verilog or SpinalHdl. And for connection of IP catalog components, AHDL is second only to block editor And above all Intel's support for AHDL in Quartus is... I have nothing to complain.
Just imagine combining this brevity with a live graphical WYSWYG editor. And the final output will be Verilog. And when the engineer looks a the generated code, he will jump for joy and cry - Hey VisualAHDL where were you all these days?
I see a small window of opportunity. Before SpinalHdl or Chisel or some other Python Verilog generators dominate main stream HDL design entry, Intel has an opportunity to over take these new languages with a brand new paradigm for design entry - VisualAHDL.
A note on High Level Synthesis. I tired it a year back (my posts in this forum are the evidence) and gave it up. It is like an auto router for PCB!!
And if openCL is great why no one designed a RiscV in OpenCL and bagged the first prize?
I strongly believe low level design entry is there to stay.
Ravi Ganesh
Regular ContributorNo Verilog coder would write it like that. It would more likely be:
wire [15:0] data = {16{nCE}};
But that example is way too contrived. How about a simple 8b counter module with an async low reset:
module count (input wire clk, input wire rst, output reg [7:0] cnt); always @(posedge clk or negedge rst) if (!rst) cnt <= 0; else cnt <= cnt+1; endmodule
But the real point is AHDL is dead and is going nowhere. Only Altera ever used it, and they basically killed it years ago. RIP.
As to OpenCL, you may not like it, but it opens up FPGA design to non-hardware engineers. Sure programming in assembly language (ie, AHDL) is fun and efficient in terms of gates. But it is very inefficient in terms of time and manpower requirements. For the same reason compilers and high level languages are the standard methodology in software development, and not programming in assembly language, as it is much more efficient in terms of manpower and productivity.
