Honored ContributorI am designing a new board with 5CEFA5F23I7 device.
Can you please explain what is the difference between a general clock input for example pins : H16,H15 - CLK11p,CLK11n to the clock inputs :CLK8p,FPLL_TL_FBp,CLK8n,FPLL_TL_FBn --PINS E10,F9. Or CLK0n,FPLL_BL_FBn,CLK0p,FPLL_BL_FBp ---PINS M8,M9. thanks
Honored ContributorDifferent pins drive different clocks in different regions. See figure 4-1 here:
https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-v/cv_5v2.pdf Then, skip to Figure 4-18 in the same document to see how different pins connect to different PLL's. Altera provides a design guide: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an662.pdf The section "Clock Planning" on page 26 says: --- Quote Start --- Understand your device’s available clock resources and correspondingly plan the design clocking scheme. Consider your requirements for timing performance, and how much logic is driven by a particular clock --- Quote End --- Which is a fancy way of saying: for your application, maybe you don't care at all about the differences between the clock pins. Or maybe you care A LOT!Honored Contributorsorry , I still don't understand what is the difference
Honored ContributorThe difference between the pins is they connect to different set of clock resources.
If you don't care which clock resource you are connecting to, then you don't care about the differences between the pins. The topic can be either extremely important (critical) or it can be "don't care" for many applications.Honored ContributorLets say that I need a free running clock source from external pin. but all general clocks are taken.
Can I use FPLL_TL_FBp ?? what are the performance difference? Do you have an example where FPLL_TL_FBp can't be used?
