the difference between a general clock inputs

Different pins drive different clocks in different regions. See figure 4-1 here:

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-v/cv_5v2.pdf

Then, skip to Figure 4-18 in the same document to see how different pins connect to different PLL's.

Altera provides a design guide:

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an662.pdf

The section "Clock Planning" on page 26 says:

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Understand your device’s available clock resources and correspondingly plan the design clocking scheme. Consider your requirements for timing performance, and how much logic is driven by a particular clock

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Which is a fancy way of saying: for your application, maybe you don't care at all about the differences between the clock pins. Or maybe you care A LOT!