test bench problem

does "infile1.txt" exist? is it being read correctly? with your code, if there is a problem with the file there is no message telling you this, it just skips the input code.

Try adding this to your infile process:

assert (not ENDFILE(inFile) ) report "Reached end of file or there was an error" severity failure.

also, with your code, a meta value on the input_tmp would return a 0 to rxn_re.

Btw, its a bad habit to leave large bits of code commented out.

And Please use the code tags around your code next time.

I have used that code style for a decade and it always works.

Now, is your file there and correct format. Are you looking at first node that acquires data from file... you need to follow the problem step by step.

sir, i have moidfied my code as per youe advice .but in waveform i get "0 " values for iput & output. i have done the simulation for 1000us.plz help:cry:.i have attched the output waveform . code is here...

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

USE IEEE.STD_LOGIC_TEXTIO.ALL;

USE STD.TEXTIO.ALL;

ENTITY x_tb_rfft IS

END x_tb_rfft;

ARCHITECTURE behavior OF x_tb_rfft IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT rfft_core

PORT(

rxn_re : IN std_logic_vector(7 downto 0);

rxn_im : IN std_logic_vector(7 downto 0);

rsclr : IN std_logic;

rce : IN std_logic;

rclk : IN std_logic;

rstart : IN std_logic;

runload : IN std_logic;

rfwd_inv : IN std_logic;

rfwd_inv_we : IN std_logic;

rxk_re : OUT std_logic_vector(18 downto 0);

rxk_im : OUT std_logic_vector(18 downto 0);

rxn_index : OUT std_logic_vector(9 downto 0);

rxk_index : OUT std_logic_vector(9 downto 0);

rrfd : OUT std_logic;

rbusy : OUT std_logic;

rdv : OUT std_logic;

redone : OUT std_logic;

rdone : OUT std_logic

);

END COMPONENT;

--Inputs

signal rxn_re : std_logic_vector(7 downto 0) := (others => '0');

signal rxn_im : std_logic_vector(7 downto 0) := (others => '0');

signal rsclr : std_logic := '0';

signal rce : std_logic := '1';

signal rclk : std_logic := '0';

signal rstart : std_logic := '0';

signal runload : std_logic := '0';

signal rfwd_inv : std_logic := '1';

signal rfwd_inv_we : std_logic := '0';

--Outputs

signal rxk_re : std_logic_vector(18 downto 0);

signal rxk_im : std_logic_vector(18 downto 0);

signal rxn_index : std_logic_vector(9 downto 0);

signal rxk_index : std_logic_vector(9 downto 0);

signal rrfd : std_logic;

signal rbusy : std_logic;

signal rdv : std_logic;

signal redone : std_logic;

signal rdone : std_logic;

SIGNAL newValueRead : BOOLEAN := TRUE;

SIGNAL newValueToSave : BOOLEAN := FALSE;

--signal count : std_logic_vector (10 DownTo 0) :="00000000000" ;

signal No_of_elements_read : integer := 0;

SIGNAL result : std_logic_vector (37 DownTo 0) := "00000000000000000000000000000000000000";

--Constants

constant PERIOD : time := 20 ns;

constant DUTY_CYCLE : real := 0.5;

constant OFFSET : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: rfft_core PORT MAP (

rxn_re => rxn_re,

rxn_im => rxn_im,

rsclr => rsclr,

rce => rce,

rclk => rclk,

rstart => rstart,

runload => runload,

rfwd_inv => rfwd_inv,

rfwd_inv_we => rfwd_inv_we,

rxk_re => rxk_re,

rxk_im => rxk_im,

rxn_index => rxn_index,

rxk_index => rxk_index,

rrfd => rrfd,

rbusy => rbusy,

rdv => rdv,

redone => redone,

rdone => rdone

);

---clock: PROCESS -- clock process for clk

---- BEGIN

--WAIT for OFFSET;

----- CLOCK_LOOP : LOOP

------- rclk <= '0';

------- WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));

------ rclk <= '1';

--------count<=count+"00000000001";

----------if (count="11111100000") THEN

------- WAIT; -- wait for ever.

-------- end if;

------ WAIT FOR (PERIOD * DUTY_CYCLE);

----------- END LOOP CLOCK_LOOP;

------END PROCESS clock;

rclk <= not rclk after 10 ns;

generate_rst_fwd_inv_we_n_start: process

begin

WAIT for OFFSET;

rsclr <='1';

rstart<='1' after 20 ns;

rstart<='0' after 40 ns;

wait until (rising_edge(rclk));

----wait for PERIOD;

-------rsclr <='0';

----rfwd_inv_we<='1';

--wait for PERIOD;

---rstart<='1';

---rfwd_inv_we<='0';

---wait for PERIOD;

----rstart<='0';

-----wait;

end process;

readProcess :PROCESS (rclk) is

file inFile:TEXT open READ_MODE is "infile1.txt";

VARIABLE inLine : LINE;

variable input_tmp : integer := 0;

------ variable ar_var : std_logic_vector (7 DownTo 0);

-------- variable ai_var : std_logic_vector (7 DownTo 0):= (others =>'0');

begin

if(rising_edge(rclk))then

if rrfd = '1' then

if not endfile(inFile)then

readline(inFile,inline);

read(inLine,input_tmp);

rxn_re <= std_logic_vector(to_signed(input_tmp,8));

end if;

end if;

end if;

end process;

------ WAIT UNTIL (rclk = '1' AND rclk'EVENT);

-----IF (NOT ENDFILE(inFile)) and rrfd ='1' THEN --(NOT ENDFILE(inFile)) and rrfd

------ READLINE(inFile, inLine);

------- READ(inLine, ar_var);

-- READ(inLine, ai_var);

-----rxn_re(7 downto 0)<=ar_var;

--- rxn_im(7 downto 0)<=ai_var;

----- No_of_elements_read <= No_of_elements_read+1;

------END IF;

--------END PROCESS readProcess;

result <= rxk_re & rxk_im;

OutputControl: PROCESS(rclk) --output the result at right time.

BEGIN

if rdv='1' then

newValueToSave <= TRUE;

else

newValueToSave <= FALSE;

end if;

end process OutputControl;

Generate_unLoadSignal: process--(rclk) -- assert unload signal pulse.

begin

-----wait until (rclk = '1' and rclk'event);

------if ( rbusy = '1' and redone = '1') then

-------runload <= '1';

---else

----runload <='0';

-------end if;

if rdone'event and rdone= '0' then

runload <= '1';

wait for PERIOD;

else

if rdone='0' then

runload <= '0';

end if;

end if;

wait on rclk;

end process Generate_unLoadSignal;

WriteProcess : PROCESS

file outFile:TEXT open WRITE_MODE is "outfile1.txt";

VARIABLE outLine : LINE;

BEGIN

WAIT UNTIL rclk = '1' AND rclk'EVENT;

IF (newValueToSave = TRUE) THEN

WRITE(outLine, result, right, 38);

WRITELINE(outFile, outLine);

END IF;

END PROCESS WriteProcess ;

END;

file:///C:/Documents%20and%20Settings/Debolina/Desktop/wvft.JPG

Are you saying your read is reading one data only?

try this

process(clk)
file file_in : text open read_mode is "datain.txt";
variable line_in : line;
variable input_tmp : integer := 0;
begin
if(rising_edge(clk))then
 if read_input = '1' then
   if not endfile(file_in)then
      readline(file_in,line_in);
      read(line_in,input_tmp);
      data_in <= std_logic_vector(to_signed(input_tmp,16));
   end if;
 end if;
end if;
end process;