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Altera_Forum's avatar
Altera_Forum
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14 years ago

test bench problem

sir, i have written a test bench code for my fft processor.here i used .text to import input data into test bench.vhd,but in output it shows only one input through out the simulation cycle. below...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Are you saying your read is reading one data only?

try this 


process(clk)
file file_in : text open read_mode is "datain.txt";
variable line_in : line;
variable input_tmp : integer := 0;
begin
if(rising_edge(clk))then
 if read_input = '1' then
   if not endfile(file_in)then
      readline(file_in,line_in);
      read(line_in,input_tmp);
      data_in <= std_logic_vector(to_signed(input_tmp,16));
   end if;
 end if;
end if;
end process;