Forum Discussion
Honored ContributorSystem ID issue
Hi everyone,
I am working in a project using Quartus v11.0. The Bsp was created using Qsys. *obs: The project was updated/converted from SOPC Builder to Qsys... So, I am having problems to load the application into the FPGA. Attached is the problem that I have. No System ID found and timestamp. I have a feeling that the problem is based on my BSP file. Because, the flash programmer cant see the System ID (probally NOT a software issue...so). Did anyone had this experience before?? What all I need to have in Qsys to set he system ID?? Thank You very much12 Replies
Altera_ForumDo you have the system ID component in the QSys project? Did you upload the image in the FPGA before using the Nios programmer?
- Altera_Forum
Yes I do have a system ID component, and I did upload the image (.sof).
Is there anything else I might be missing? Thank You - Altera_Forum
I just talked to someone, and he told me that I need to have the .qip file added into my Quartus project, then compile. Does that proceed?!
If so, I wonder if the qip file gets created on Qsys. Because I am not getting it. Is there any file created by Qsys, that should be added to the project to set IDs? Thanks - Altera_Forum
IIRC QSys generates its files in a specific directory inside the Quartus project. The qip file should be there.
As it was a project converted from SOPC Builder, maybe Quartus is still using the SOPC builder project instead of QSys... - Altera_Forum
I had to delete the old folders so then the file could get updated. It didn't solved my problem though.
I would like to make sure that the sysID is there. Is there anyway I can make sure that the sysID component is inside my BSP? (maybe lookiing into system.h!?) Thanks - Altera_Forum
If the system ID is in the BSP then you should see some definitions for it. If for example you called it system_id in QSYS, then you should find a group of definitions starting with SYSTEM_ID (SYSTEM_ID_NAME, SYSTEM_ID_BASE, etc.)
- Altera_Forum
I found it there, I attached what I have there. Does that look right, what else could I check/fix?
Thanks - Altera_Forum
check again and again that you compile the correct project and that the .sof file you put in the FPGA is the one you just compiled and not something else.
Check that your BSP project points to the correct .sopcinfo file and not the one from another project. Check in QSys that the System ID component is connected to the Nios CPU data master. If the System ID component is running on a different clock than the CPU, check that this clock is active. You can also try to access directly the System ID component through System Console, as explained in this thread (http://www.alteraforum.com/forum/showthread.php?t=36930). In your case you'd have to change the addresses, so it would be something likeset mast 0] open_service master $mast processor_reset $mast master_read_32 $mast 0x00400800 1 master_read_32 $mast 0x00400804 1 - Altera_Forum
Thank you for your help. I am not really sure how to check if the clock is active through the console. However I ran the script and it gave me some information back but how does that help me?
I got : master_read_32 $mast 0x00400800 1 0x01440004 master_read_32 $mast 0x00400804 1 Thanks 0x297ff804 - Altera_Forum
The first return value is supposed to the the ID and the second one the timestamp.
None of the value seems even remotely close to what you have in your BSP or your first screenshot. This indicates that what you currently have in the FPGA isn't the image expected by your BSP. So check that both the BSP and the Quartus project are using the same QSys project, compile the QSys project first, then the Quartus project and the software, check that you put the correct .sof file and try again to upload your software.
