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Altera_Forum's avatar
Altera_Forum
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14 years ago

System ID issue

Hi everyone, I am working in a project using Quartus v11.0. The Bsp was created using Qsys. *obs: The project was updated/converted from SOPC Builder to Qsys... So, I am having pro...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

check again and again that you compile the correct project and that the .sof file you put in the FPGA is the one you just compiled and not something else.

Check that your BSP project points to the correct .sopcinfo file and not the one from another project.

Check in QSys that the System ID component is connected to the Nios CPU data master.

If the System ID component is running on a different clock than the CPU, check that this clock is active.

You can also try to access directly the System ID component through System Console, as explained in this thread (http://www.alteraforum.com/forum/showthread.php?t=36930). In your case you'd have to change the addresses, so it would be something like
set mast  0]
open_service master $mast
processor_reset $mast
master_read_32 $mast 0x00400800 1
master_read_32 $mast 0x00400804 1