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Altera_Forum
Honored Contributor
Honored Contributorsystem console, external memory, multiple masters
Hi guys
Im fairly new here. Im working with a cyclone V GX board and have used qsys to add a memory controller in my nios code to control some lpddr memory on the eval board. Im using system console to write some values to the memory, but i notice that system console finds 2 masters: the memory and the nios. I can use system console to write to the memory using the valid address values that qsys assigned, but i need to use the master assigned to the memory (not nios). My problem is that i need nios to access what i write to external memory. In my nios code, i try read that same valid address that points to my lpddr memory, but its not the same as what i wrote with system console. I was under the impression that the "avalon memory master" would take care of letting nios see that memory. Am i missing something in my qsys system? Im trying to learn everything at once :) Can you guys help me understand what i need to do? I can post code/screenshots if needed thanks!!!!47 Replies
Altera_Forum--- Quote Start --- Ive actually went ahead and abandoned the write_from_file idea. i put a gigantic for loop in my tcl script that loops over a ton of write_32 mem write --- Quote End --- You didn't read my Avalon Analysis document then? https://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_analysis.pdf master_read/write_memory are the most efficient routines. You could simply read a file into a Tcl variable and then use master_write_memory to write it. That is what I use (the master_read/write_file routines are new). --- Quote Start --- that i thought for sure would be just as memory intensive as write_from_file and the nios code didnt lock up and triggered perfectly. --- Quote End --- There is nothing memory intensive about the JTAG interface. Its really slow. The JTAG clock is around 6MHz, and it takes about 10 clock periods per byte (the clock duty cycle is not 50-50). A 32-bit write packet involves a header, the address, and the write data, so its 10s of bytes. That means your Avalon-MM accesses are in the kHz rate. The NIOS processor and JTAG to Avalon-MM master have plenty of time to arbitrate and access a common slave memory device. --- Quote Start --- so there has got to be a bug in that write from file that hoses mem. --- Quote End --- Yes, most likely. However, the bug may not be in the FPGA, it may be in the software on the PC. --- Quote Start --- but, i dont have time to wait for altera right now, ive got to get this up and running so we can capture data from these DUTs. ill send what i have to altera. if they either correct me or fix a bug, ill post here --- Quote End --- I've given you a few suggestions, many of which I know work, so you should be able to get something working. Cheers, Dave- Altera_Forum
Hi Dave
Sorry for the confusion. I meant i was abandoning the master_write_from_file and just loop over the memory_write_32 commands to fill the memory thanks - Altera_Forum--- Quote Start --- Sorry for the confusion. I meant i was abandoning the master_write_from_file and just loop over the memory_write_32 commands to fill the memory --- Quote End --- Yep, I understood that. However, master_write_32 is slow compared to master_write_bytes. Check out the SignalTap II traces in the document I referred to above. You'll gain a performance increase (shorter download time) if you change to master_write_bytes. Cheers, Dave
- Altera_Forum
Hey Dave
I see what you mean about the master_write_32 vs master_write_memory speed. wow. big difference!! thanks for that tip!! but, the other reason im writing back is that even though ive added the jtag avalon memory master, the nios still doesnt see whats written in the lpddr mem on my board. Can you look at my qsys diagram and see if im missing something? Im going to try connecting the master port of the MM to the debug_mem_slave of the nios to see if that helps. im still a little fuzzy on when/when not to make connections in qsys. thanks!! - Altera_Forum--- Quote Start --- I see what you mean about the master_write_32 vs master_write_memory speed. wow. big difference!! thanks for that tip!! --- Quote End --- You're welcome! --- Quote Start --- but, the other reason im writing back is that even though ive added the jtag avalon memory master, the nios still doesnt see whats written in the lpddr mem on my board. Can you look at my qsys diagram and see if im missing something? --- Quote End --- Sure - why don't you screen shot it and post the image. The image you posted in Post#3 connects the NIOS II instruction and data master to the LPDDR, so the processor should see the LPDDR at the address you have specified. When you say that the NIOS II processor does not see the LPDDR, what are you using to read memory? Eg., are you using NIOS II code and printing to either a serial port or JTAG UART? If you are using SystemConsole to connect to the NIOS II JTAG connections, then I'm not sure what you're supposed to see, as I do not use those interfaces. The NIOS II IDE debugger should see the correct memory locations though. Cheers, Dave
- Altera_Forum
Hey Dave
I think connecting the master to the nios debug_mem_slave got it working. But, my nios code freezes in the trigger loop when using the system console faster master_write_memory to fill lpddr mem. the code will not freeze when using master_write_32, but freezes with master_write_memory and master_write_from_file. but its waay too slow. 1 step forward, 2 steps back :) ive written to altera as well. thanks - Altera_Forum--- Quote Start --- I think connecting the master to the nios debug_mem_slave got it working. --- Quote End --- Ok, a step forward ... --- Quote Start --- But, my nios code freezes in the trigger loop when using the system console faster master_write_memory to fill lpddr mem. the code will not freeze when using master_write_32, but freezes with master_write_memory and master_write_from_file. but its waay too slow. 1 step forward, 2 steps back :) --- Quote End --- Not at all. This just tells you that your master_write_memory blocks are too large. Rather than writing the whole block of data in one write, chop it up into 1K blocks, and I suspect it will work. The other thing you can do is look at the arbitration shares/priorities. Elevate the priority of the master that is getting locked out. To see the arbitration shares select a component, eg., one of your masters, right click, and select "Show arbitration shares". I forget the meaning of the shares numbers, read the docs now that you know what to look for. Cheers, Dave
- Altera_Forum
Hi Dave
I appreciate your suggestions. I did try to increase the arbitration shares on the path from the nios to the lpddr memory. Bumped it to 50 (i saw that in a tutorial so i tried it). It had no effect. nios still freezing. I also tried just writing 200 commands at a time (800 bytes) and it seemed to work. no freezing. But then i realized that i needed to increment the memory address in master_write_memory to keep from just overwriting the same memory space and the freezing came back. So it seems like i might be writing into some illegal memory, but my code respects the qsys addresses. all of my instructions are written into x00000010 - x00010010 and ive tried my trigger at both x00000000 (lpddr) and x20000000 (on chip). Any ideas? thanks - Altera_Forum--- Quote Start --- Any ideas? --- Quote End --- 1. Simulate the design. 2. SignalTap II the design. The second option would probably be the easiest to start with. The question is what would you use as the trigger? You'd have to determine a trigger condition that allowed you to see something useful. Cheers, Dave
- Altera_Forum
Ive started looking at signalTap. Altera told me to trigger on nothing and run it after the nios froze up, but the instruction stored in the instruction addr doesnt match anything in the object/assembly instructions, so ive asked them about that.
ill keep messing with it. i wonder if i could have the nios monitor the bytestream for a trigger instead of monitoring memory? And trigger over the bytestream? Do you have any experience with bytesteam in system console? thanks
