Honored Contributoralways @(posedge clk or negedge rst)begin
if(!rst)begin ..... end else begin if(a) .... if(b) .... if(c) .... end end I found that the synthesised circuit is priority,i.e.there are selectors.But I want them to be parallel!How can I do with that? Please!
Honored ContributorVerilog states cases statements are priority encoded. If it's obvious it doesn't need priority, synthesis can often figure it out. Historically most people got around this with parallel_case and full_case attributes. System verilog now has "unique" and "priority" attributes. I'm sure there are some nice quick descriptions on the web/wikipedia that describe those two. If you want the long explanation, go to:
http://www.sutherland-hdl.com/papers/2005-snug-paper_systemverilog_unique_and_priority.pdfHonored Contributorthank u!
But I don't mean the "case" sentence.so parallel_case and full_case attributes don't help. I got the situation that 8 "if" sentences need to be included in the always block,so the priority circuit decreases the fmax. I have to make them parallel so that increase the Fmax.Honored ContributorYou should clarify in which regard you mean priority is involved with the present construct. I don't see any priority related behavior at all. It may be of course, if the conditional expressions are setting the same variables.
Honored ContributorYes,I set the same variable in the three conditional expressions.Is that the problem?
Honored ContributorYes by making multiple assignments in an if cascade you ended up coding priority into the assignment. You could do a one-hot mux like this assuming a, b, and c are asserted mutually exclusively:
always @ (a or b or c)
begin
case ({c, b, a})
3'b001: <expression>;
3'b010: <expression>;
3'b100: <expression>;
default: <expression>; // this case can never happen if only one of a, b, or c are ever enabled at any given time
endcase
end
Thank U so much! It's helpfull!!
Honored ContributorThank U so much! It's helpfull!!
--- Quote Start --- Yes by making multiple assignments in an if cascade you ended up coding priority into the assignment. You could do a one-hot mux like this assuming a, b, and c are asserted mutually exclusively:always @ (a or b or c)
begin
case ({c, b, a})
3'b001: <expression>;
3'b010: <expression>;
3'b100: <expression>;
default: <expression>; // this case can never happen if only one of a, b, or c are ever enabled at any given time
endcase
end
Make sure though that only A, B, or C can be asserted at any given time, otherwise that "one-hot" encoding will fail and the default case will be used. In other words, using the example above if C,B,A (concatenated together) came out to anything but 001, 010, or 100, then the default expression would be decoded.
Honored ContributorIn SystemVerilog you can use the unique attribute to if else if else statement.
always @(posedge clk or negedge rst)begin
if(!rst)begin
.....
end
else begin
unique if(a)
....
else if(b)
....
else if(c)
....
end
end
