synthesis of several "if..if...if "sentence.

In SystemVerilog you can use the unique attribute to if else if else statement.

always @(posedge clk or negedge rst)begin
  if(!rst)begin
  .....
  end
  else begin
    unique if(a)
      ....
    else if(b)
      ....
    else if(c)
      ....
  end
end