Forum Discussion

Honored Contributor

14 years ago

synthesis of several "if..if...if "sentence.

always @(posedge clk or negedge rst)begin if(!rst)begin ..... end else begin if(a) .... if(b) .... if(c) .... end end I found tha...

Honored Contributor

14 years ago

thank u!

But I don't mean the "case" sentence.so parallel_case and full_case attributes don't help.

I got the situation that 8 "if" sentences need to be included in the always block,so the priority circuit decreases the fmax.

I have to make them parallel so that increase the Fmax.