synthesis of several "if..if...if "sentence.

Verilog states cases statements are priority encoded. If it's obvious it doesn't need priority, synthesis can often figure it out. Historically most people got around this with parallel_case and full_case attributes. System verilog now has "unique" and "priority" attributes. I'm sure there are some nice quick descriptions on the web/wikipedia that describe those two. If you want the long explanation, go to: