Honored Contributorhello
i have ciclon 2 fpga module. I want to ask is it possible to be synthesed module which react on chenage of signal (not on positive or negativ edge ) using if (clk'event ) insted if (clk'event and clk = '1')
Honored ContributorNo, the synthesizer needs either a rising edge of a clock, or a falling edge. You can't use both.
Second this should only be used on an actual clock. If you want to monitor changes on a signal, it would be better to sample it using a real clock and compare it with its previous value.Honored ContributorIt's not a good habit to use both posedge and negedge of one clock.
Honored ContributorMore than that, it just isn't synthesizable in Quartus.
