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Altera_Forum's avatar
Altera_Forum
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16 years ago

synthesis of modul reacting of signal change

hello i have ciclon 2 fpga module. I want to ask is it possible to be synthesed module which react on chenage of signal (not on positive or negativ edge ) using if (clk'event ) inste...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

It's not a good habit to use both posedge and negedge of one clock.