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Altera_Forum
Honored Contributor
Honored Contributorsynthesis of modul reacting of signal change
hello i have ciclon 2 fpga module. I want to ask is it possible to be synthesed module which react on chenage of signal (not on positive or negativ edge ) using if (clk'event ) inste...
Altera_ForumHonored Contributor
Honored ContributorNo, the synthesizer needs either a rising edge of a clock, or a falling edge. You can't use both.
Second this should only be used on an actual clock. If you want to monitor changes on a signal, it would be better to sample it using a real clock and compare it with its previous value.
