Honored ContributorI have got timing problems with a ACEX1K30 Design. To solve my problems I want to change my design in a synchronous design (only one global clock).
Where can I find examples for synchronous designs? I use the Quartus (Web-Edition) graphical editor (no VHDL or HDL, sometimes AHDL). I have to realize: Eventcounter (up/down), Ratemultiplier, Frquency-Divider, Monoflop, Timer (Shiftregister), Data Register (from µC).
Honored ContributorI suggest you google with the following words.
Verilog Synchronous design or Vhdl Synchronous design This will provide much help for you.Honored ContributorI suggest you the vhdl instruction
if clk'event and clk = 1 the vhdl (or verilog) language guarantee to you about freedom degrees...some things with these graphical tools is much more complicate.... smile stefania:)Honored ContributorThank you Avatar, I will try but I think I will have problems with understanding VHDL or Verilog HDL.
Honored ContributorHi Helmut,
what kind of Problem you have? What forfrequencies are needed? Do you use you global the Clock Input?In my first Time i wrote also all in AHDL.Honored Contributor
