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Honored Contributor
Honored ContributorSynchronous Design
I have got timing problems with a ACEX1K30 Design. To solve my problems I want to change my design in a synchronous design (only one global clock). Where can I find examples for synchronous desig...
Altera_ForumHonored Contributor
Honored ContributorI suggest you the vhdl instruction
if clk'event and clk = 1 the vhdl (or verilog) language guarantee to you about freedom degrees...some things with these graphical tools is much more complicate.... smile stefania:)
