Honored ContributorI have two clocks coming to my FPGA through external source:
1) Fast clock 2) Slow clock. Internally, another clock is generated out of the fast clock through a divide by 10 counter. Now, my requirement is to synchronize this divide by 10 clock and the slow clock. Any ideas, how it can be done?
Honored ContributorYour idea is wrong by itself. First of all You don't want to use gated clocks - that's a bad idea. Secondly, what do You do with data, that You need to sync two clocks? Sounds like kind of mess...
Honored ContributorWhat do you mean with 'synchronize'?
Depending on the desired synchronisation and the involved frequencies, you could possibly resample the divide-by-10 output with the slow clock. If the two clock signals are to be used outside fpga, a logic-based solution can be used. Instead, if they are supposed to be used as 'real' clocks inside the fpga, you should consider using a PLL, or a single fast clock and a chip enable strobe for slower components.Honored ContributorYou can get a synchronisd copy of the 'slow clock' (as a signal, not a clock) by using a series of 2 (do you need 3?) latches on successive clock edges.
The output of the first latch is likely to be metastable and might oscillate, hopefully they have died down by the second clock edge.
