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Honored Contributor
Honored ContributorSynchronizing two different clocks
I have two clocks coming to my FPGA through external source: 1) Fast clock 2) Slow clock. Internally, another clock is generated out of the fast clock through a divide by 10 counter. Now,...
Altera_ForumHonored Contributor
Honored ContributorYou can get a synchronisd copy of the 'slow clock' (as a signal, not a clock) by using a series of 2 (do you need 3?) latches on successive clock edges.
The output of the first latch is likely to be metastable and might oscillate, hopefully they have died down by the second clock edge.
