Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorSynchronizing two different clocks
I have two clocks coming to my FPGA through external source: 1) Fast clock 2) Slow clock. Internally, another clock is generated out of the fast clock through a divide by 10 counter. Now,...
Altera_ForumHonored Contributor
Honored ContributorWhat do you mean with 'synchronize'?
Depending on the desired synchronisation and the involved frequencies, you could possibly resample the divide-by-10 output with the slow clock. If the two clock signals are to be used outside fpga, a logic-based solution can be used. Instead, if they are supposed to be used as 'real' clocks inside the fpga, you should consider using a PLL, or a single fast clock and a chip enable strobe for slower components.
