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Rk_Athram's avatar
Rk_Athram
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Supporting DDR4(MTA72ASS8G72LZ ) for 10AX057N3F40E2SG

Hi,

Does DDR4 MTA72ASS8G72LZ will support arria10 FPGA(10AX057N3F40E2SG ) ?

2 Replies

    • Rk_Athram's avatar
      Rk_Athram
      Icon for Occasional Contributor rankOccasional Contributor

      Hi,
      Thank you for the response.

      MTA72ASS8G72LZ is 2666Mhz, as per Arria10 device it will support maximum of 2400.
      so we have chosen to work with 2133Mhz.
      From EMIF existing template we have matched timing data with data sheet it was proper.

      As latency and timing are downgraded/taken with respect to 2133 speed.

      serial presence data for LRDIMM, default values(which are accurate with template) should be consider exiting values
      SPD byte 137 : 0x65
      SPD byte 138 :0x05

      as per datasheet (https://in.micron.com/products/dram-modules/lrdimm/part-catalog/mta72ass8g72lz-2g6)

      SPD byte 137 : 0x75
      SPD byte 138 :0x0A

      MTA72ASS8G72LZ-2G6B2137DDR4-REG OUTPUT DRIVE FOR CONTROL75
      MTA72ASS8G72LZ-2G6B2138DDR4-REG OUTPUT DRIVE FOR CLOCK0A

      So the question is

      Which SPD values we needed to set in IP?

      do we need to go with Datasheet or template values ?

      what will the effect on data transfer/reception ?



      Regards,

      Rajesh