Stratix10 PCIe clock structure issue

Hello everyone，

I am using quartus Pro 22.3 , device ( stratix10 1SX110HN2F43I2VG ) , IP core ( L-Tile and H-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express 22.2.0, GEN 3X4 125Mhz.

ug_s10_pcie_avmm-683667-666643 shows that The Intel L-/H-Tile Avalon-MM for PCI Express IP supports the Separate Reference Clock With No Spread Spectrum architecture (SRNS), but not the Separate Reference Clock With Independent Spread Spectrum architecture (SRIS).

When I use the Common Clock Architecture (pcie reference clock come from the PC board through the Oculink interface), everything is normal and the example design can run successfully. But when I modify the pin constraints and use a 100M local clock from the FPGA board, Linux kernel will continue to print errors and the example design cannot run normally.

I don't think these clocks are spread spectrum clocks, what could be the possible reason for this ?