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allen18's avatar
allen18
Icon for Occasional Contributor rankOccasional Contributor
10 months ago

Stratix10 PCIe clock structure issue

Hello everyone， I am using quartus Pro 22.3 , device ( stratix10 1SX110HN2F43I2VG ) , IP core ( L-Tile and H-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express 22.2.0, GEN 3X4 125Mhz. ug...
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VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
10 months ago

Hi allen18,


Yes, Stratix 10 L-/H-Tile PCIe IP does not support SRIS, and the on-board oscillator is not used for PCIe.

Please use the SRNS or Common Reference Clock with Spread Spectrum Clocking architecture instead.


Additionally, please ensure both the RP and EP sides of the link disable the spread spectrum if using the separate clock architecture.


KDB: https://www.intel.com/content/www/us/en/support/programmable/articles/000075574.html


Thanks.

Best Regards,

Ven


  • allen18's avatar
    allen18
    Icon for Occasional Contributor rankOccasional Contributor
    10 months ago

    Hi ventt,

    I think my current application scenario should be SRNS，why the on-board oscillator is not used for PCIe reference clock ?