STRATIX10 GX device : 1SG280HNF43 with JTAG ID CODE : 0xC32250DD CLK PINS don't work.

Question

Hello,I have a STRATIX10 GX device :
1SG280HNF43 with JTAG ID CODE :
0xC32250DD
I have tried multiple clocks from the datasheet for this device but I'm unable to see any sample data. All I see are X's in the waveform.

Here are some of the clocks I have tried for this board:
BA22
BG28
AM41
AK41
BH33
AY9

Can you please help us figure out a CLK pin for this board that we can use as our PLL source.

engwei_o_intel · Answer

Hi there
May I know if your FPGA has entered user mode? Did you check if you have a clean source clock? Are you using signalTap and at which node you are seeing X's in the waveform? Do you have simulation run for your design? For clock connection, you can check on the pin functionality in pin connection guideline:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/stratix-10/pcg-01020.pdf
and also you can check on the pinout files here to match with the description in pin connection guideline:
https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html
Or you can also have a view and make assignment in pin planner.
Thanks.
Eng Wei

app_engineer · Answer

Hello,Thank you for responding. We purchased the Stratix10 GX development kit and we were assuming the part number will be 
1SG280HU2F50E2VG.
When we used this part number, we got an error that the JTAG ID codes do not match while programming.
So we isolated the JTAG id code which is 0xC32250DD and found that the part number could be :
1SG280HNF43 from 
https://bsdl.info/details.htm?sid=10b82bfd8620771788ca59b002289d77
 
Is this correct?
 
We are generating the waveform using Synopsys in house tools and don't see valid sample data. for the clocks mentioned above.

engwei_o_intel · Answer

Hi there
I am not the expert in JTAG Programming. I realize you have another thread discussing on it, perhaps you can continue to get the confirmation in the thread:
https://community.intel.com/t5/Programmable-Devices/Quartus-PGM-Error-help-Expected-JTAG-ID-code-0x032250DD-for/td-p/1225551

We need to make sure the FPGA is in user mode, before we looking for clock sample data. And also at which node you get the sample data?

Thanks.
Eng Wei

app_engineer · Answer

Hello,How do I ensure the board is in user mode. Is there a switch I need to toggle physically on the board. I'm capturing sample using our in house synopsys tools. But the sample data on hw shows X's which I presume is because of the sampling clock not getting to the bus.

engwei_o_intel · Answer

Hi there
Sorry for late response due to my extended holidays. We can check the INIT_DONE signal to make sure the configuration is done and enter user mode.
We can refer to the flow is below doc:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-config.pdf

thanks.
Eng Wei

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STRATIX10 GX device : 1SG280HNF43 with JTAG ID CODE : 0xC32250DD CLK PINS don't work.

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