Forum Discussion
Hello,
Thank you for responding. We purchased the Stratix10 GX development kit and we were assuming the part number will be
https://bsdl.info/details.htm?sid=10b82bfd8620771788ca59b002289d77
Is this correct?
We are generating the waveform using Synopsys in house tools and don't see valid sample data. for the clocks mentioned above.
Hi there
I am not the expert in JTAG Programming. I realize you have another thread discussing on it, perhaps you can continue to get the confirmation in the thread:
We need to make sure the FPGA is in user mode, before we looking for clock sample data. And also at which node you get the sample data?
Thanks.
Eng Wei
- app_engineer5 years ago
New Contributor
Hello,
How do I ensure the board is in user mode. Is there a switch I need to toggle physically on the board. I'm capturing sample using our in house synopsys tools. But the sample data on hw shows X's which I presume is because of the sampling clock not getting to the bus.- EngWei_O_Intel5 years ago
Frequent Contributor
Hi there
Sorry for late response due to my extended holidays. We can check the INIT_DONE signal to make sure the configuration is done and enter user mode.
We can refer to the flow is below doc:
thanks.
Eng Wei
- EngWei_O_Intel5 years ago
Frequent Contributor
We do not receive any response from you to the previous reply that have been provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Eng Wei