Forum Discussion
Hi there
May I know if your FPGA has entered user mode? Did you check if you have a clean source clock? Are you using signalTap and at which node you are seeing X's in the waveform? Do you have simulation run for your design? For clock connection, you can check on the pin functionality in pin connection guideline:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/stratix-10/pcg-01020.pdf
and also you can check on the pinout files here to match with the description in pin connection guideline:
https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html
Or you can also have a view and make assignment in pin planner.
Thanks.
Eng Wei
Hello,
Thank you for responding. We purchased the Stratix10 GX development kit and we were assuming the part number will be
https://bsdl.info/details.htm?sid=10b82bfd8620771788ca59b002289d77
Is this correct?
We are generating the waveform using Synopsys in house tools and don't see valid sample data. for the clocks mentioned above.
- EngWei_O_Intel5 years ago
Frequent Contributor
Hi there
I am not the expert in JTAG Programming. I realize you have another thread discussing on it, perhaps you can continue to get the confirmation in the thread:
We need to make sure the FPGA is in user mode, before we looking for clock sample data. And also at which node you get the sample data?
Thanks.
Eng Wei
- app_engineer5 years ago
New Contributor
Hello,
How do I ensure the board is in user mode. Is there a switch I need to toggle physically on the board. I'm capturing sample using our in house synopsys tools. But the sample data on hw shows X's which I presume is because of the sampling clock not getting to the bus.- EngWei_O_Intel5 years ago
Frequent Contributor
Hi there
Sorry for late response due to my extended holidays. We can check the INIT_DONE signal to make sure the configuration is done and enter user mode.
We can refer to the flow is below doc:
thanks.
Eng Wei