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DS13's avatar
DS13
Icon for New Contributor rankNew Contributor
2 years ago

Stratix V - Weak Pull Ups

Hi, I want to use a Stratix V GX (P/N: 5SGXMA5K3F40C2N) in my design. I saw on Figure 8-1 on Stratix V Handbook (Vol. 1), on "Configuration Sequence for Stratix V Devices", that all I/Os are tied ...
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AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


Thank you for reaching out Intel FPGA Community.


  1. From the handbook, it mentioned for the pull-up resistor, typically 25 kΩ.
  2. From what I understand, the weak pull-up resistor (R) in the Stratix V input/output element (IOE) is enabled during configuration download to keep the I/O pins from floating.
  3. This device is supporting Hot-Socketing Implementation which means this feature tri-state the output buffer during power up and power down of the power supplies. Hot-socketing circuitry prevents excess I/O leakage during power up. Please be noted that the hot-socketing feature is not applied to the configuration pins. Therefore, these pins will drive out during power up and power down.


Regards,

Aqid