Altera_Forum
Honored Contributor
16 years agoStratix II/III with no external oscillator
Hi
I have a Stratix II GX and Stratix III dev board setup with no external oscillator, only connections for the FPGA are the JTAG and passive serial connectors. Does anyone have any experience with either being able to use the blaster clock (ie TCK for jtag) or a synthesized clock (ie inverter ring in the FPGA) as a signaltap clock? I would like to be able to write something/anything to the FPGA and prove that it works using signaltap with this setup. Thanks for your help!