Stratix III dev kit: factory design doesn't meet timing requirements - why?

Well,

I filed a service request at Altera MySupport and this is the reply:

" Dear Sir.

This critical warning is from the fact that the ref clock in pin_t33 is not the dedicated clock pin used by the PLL on the bottom bank, you can ignore this warning message and it will not affect the function of the example design of AN435. We agree that this is a board design defect, there should be a dedicated clock input for the PLLs on the bottom bank.

PIN_T33 is the dedicated ref clock input for PLL_L2 and PLL_L3.

Regards!

Allan "

So I assume that this is a problem of the board of the development kit.

The example project (AN435) is effectively working and, excluding those critical warnings that I don't like much, I have no timing issues.

Hope this helps a little,

bye

mantoz