Stratix III dev kit: factory design doesn't meet timing requirements - why?

I've asked service request too but I still wait the answer...

But pin_T33 is a global clock which can drive throughout the entire device, so I don't really understand the problem....

Anyway I have tried to assign the input clock PLL (at Bottom1) with Pin_AN15 (GCLK7p), a dedicated clock for PLL Bottom1, but warnings are still there!!

I'd like to find the solution for this, in order to have the best design for the development of my own PCB...

Well,

I filed a service request at Altera MySupport and this is the reply:

" Dear Sir.

This critical warning is from the fact that the ref clock in pin_t33 is not the dedicated clock pin used by the PLL on the bottom bank, you can ignore this warning message and it will not affect the function of the example design of AN435. We agree that this is a board design defect, there should be a dedicated clock input for the PLLs on the bottom bank.

PIN_T33 is the dedicated ref clock input for PLL_L2 and PLL_L3.

Regards!

Allan "

So I assume that this is a problem of the board of the development kit.

The example project (AN435) is effectively working and, excluding those critical warnings that I don't like much, I have no timing issues.

Hope this helps a little,

bye

mantoz

I have the same problem as you, I don't know how to solve those critical warnings.

If someone can help us!

This topic describe a similar problem, but don't solve my problem:

http://www.alteraforum.com/forum/showthread.php?t=4621&highlight=sopc+sys+clk

I have set the input clock as global, but warnings are still there...

I followed your suggestions and tried implementing the AN435 example.

It seems to work, but I get 12 critical warnings which I would like to solve.

Critical Warning: PLL clock ddr2_dimm_inst|ddr2_dimm_controller_phy_inst|alt_mem_phy_inst|ddr2_dimm_phy_alt_mem_phy_siii_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.

Critical Warning: PLL clock ddr2_dimm_inst|ddr2_dimm_controller_phy_inst|alt_mem_phy_inst|ddr2_dimm_phy_alt_mem_phy_siii_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.

Critical Warning: PLL clock ddr2_dimm_inst|ddr2_dimm_controller_phy_inst|alt_mem_phy_inst|ddr2_dimm_phy_alt_mem_phy_siii_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.

Critical Warning: PLL clock ddr2_dimm_inst|ddr2_dimm_controller_phy_inst|alt_mem_phy_inst|ddr2_dimm_phy_alt_mem_phy_siii_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.

Critical Warning: PLL clock ddr2_dimm_inst|ddr2_dimm_controller_phy_inst|alt_mem_phy_inst|ddr2_dimm_phy_alt_mem_phy_siii_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.

Critical Warning: PLL clock ddr2_dimm_inst|ddr2_dimm_controller_phy_inst|alt_mem_phy_inst|ddr2_dimm_phy_alt_mem_phy_siii_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.

Critical Warning: PLL clock ddr2_dimm_inst|ddr2_dimm_controller_phy_inst|alt_mem_phy_inst|ddr2_dimm_phy_alt_mem_phy_siii_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.

Critical Warning: PLL clock ddr2_dimm_inst|ddr2_dimm_controller_phy_inst|alt_mem_phy_inst|ddr2_dimm_phy_alt_mem_phy_siii_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.

Critical Warning: PLL clock ddr2_dimm_inst|ddr2_dimm_controller_phy_inst|alt_mem_phy_inst|ddr2_dimm_phy_alt_mem_phy_siii_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.

Critical Warning: PLL clock ddr2_dimm_inst|ddr2_dimm_controller_phy_inst|alt_mem_phy_inst|ddr2_dimm_phy_alt_mem_phy_siii_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.

Critical Warning: PLL clock ddr2_dimm_inst|ddr2_dimm_controller_phy_inst|alt_mem_phy_inst|ddr2_dimm_phy_alt_mem_phy_siii_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.

Critical Warning: PLL clock ddr2_dimm_inst|ddr2_dimm_controller_phy_inst|alt_mem_phy_inst|ddr2_dimm_phy_alt_mem_phy_siii_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.

Looking at the fitter report, the design is using PLL_B1.

The 50MHz clock is on pin T33, which, as far as I know, is the only pin connected to the 50MHz-oscillator.

How can I solve this? I would like to start migrating my Stratix II system to Stratix III witha fully working (no critical warnings) design.

Thanks,

mantoz

The reference design did not meet timing when you compiled it, but it most certainly did when altera compiled it and provided the programming files. That means the design is capable of meeting timing, just not with the particular parameters you chose when compiling. Try changing the fitter effort, seed values, remove common clock pessimism on the timing analysis, run a seed sweep, tell it to compile for timing and not space, duplicate registers for increased timing, etc.. A lot of options can effect the outcome of the compilation, just play with them until you find a balance of compilation time and results.

Kevin

The best would be to start with the AN435: Using DDR2 in SIII device.

There is a very simple example project, page 42.

It checks read/write in memory (but not all memory in fact)