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Altera_Forum's avatar
Altera_Forum
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17 years ago

Stratix III dev kit: factory design doesn't meet timing requirements - why?

Hi all, some days ago we received our Stratix III DSP development kit, and now we are playing with it. In particular we started from the basic stuff, using the example which comes with the boa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I've asked service request too but I still wait the answer...

But pin_T33 is a global clock which can drive throughout the entire device, so I don't really understand the problem....

Anyway I have tried to assign the input clock PLL (at Bottom1) with Pin_AN15 (GCLK7p), a dedicated clock for PLL Bottom1, but warnings are still there!!

I'd like to find the solution for this, in order to have the best design for the development of my own PCB...