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Honored ContributorStratix III dev kit: factory design doesn't meet timing requirements - why?
Hi all, some days ago we received our Stratix III DSP development kit, and now we are playing with it. In particular we started from the basic stuff, using the example which comes with the boa...
Altera_ForumHonored Contributor
Honored ContributorI followed your suggestions and tried implementing the AN435 example.
It seems to work, but I get 12 critical warnings which I would like to solve. Critical Warning: PLL clock ddr2_dimm_inst|ddr2_dimm_controller_phy_inst|alt_mem_phy_inst|ddr2_dimm_phy_alt_mem_phy_siii_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Critical Warning: PLL clock ddr2_dimm_inst|ddr2_dimm_controller_phy_inst|alt_mem_phy_inst|ddr2_dimm_phy_alt_mem_phy_siii_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Critical Warning: PLL clock ddr2_dimm_inst|ddr2_dimm_controller_phy_inst|alt_mem_phy_inst|ddr2_dimm_phy_alt_mem_phy_siii_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Critical Warning: PLL clock ddr2_dimm_inst|ddr2_dimm_controller_phy_inst|alt_mem_phy_inst|ddr2_dimm_phy_alt_mem_phy_siii_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Critical Warning: PLL clock ddr2_dimm_inst|ddr2_dimm_controller_phy_inst|alt_mem_phy_inst|ddr2_dimm_phy_alt_mem_phy_siii_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Critical Warning: PLL clock ddr2_dimm_inst|ddr2_dimm_controller_phy_inst|alt_mem_phy_inst|ddr2_dimm_phy_alt_mem_phy_siii_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Critical Warning: PLL clock ddr2_dimm_inst|ddr2_dimm_controller_phy_inst|alt_mem_phy_inst|ddr2_dimm_phy_alt_mem_phy_siii_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Critical Warning: PLL clock ddr2_dimm_inst|ddr2_dimm_controller_phy_inst|alt_mem_phy_inst|ddr2_dimm_phy_alt_mem_phy_siii_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Critical Warning: PLL clock ddr2_dimm_inst|ddr2_dimm_controller_phy_inst|alt_mem_phy_inst|ddr2_dimm_phy_alt_mem_phy_siii_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Critical Warning: PLL clock ddr2_dimm_inst|ddr2_dimm_controller_phy_inst|alt_mem_phy_inst|ddr2_dimm_phy_alt_mem_phy_siii_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Critical Warning: PLL clock ddr2_dimm_inst|ddr2_dimm_controller_phy_inst|alt_mem_phy_inst|ddr2_dimm_phy_alt_mem_phy_siii_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Critical Warning: PLL clock ddr2_dimm_inst|ddr2_dimm_controller_phy_inst|alt_mem_phy_inst|ddr2_dimm_phy_alt_mem_phy_siii_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Looking at the fitter report, the design is using PLL_B1. The 50MHz clock is on pin T33, which, as far as I know, is the only pin connected to the 50MHz-oscillator. How can I solve this? I would like to start migrating my Stratix II system to Stratix III witha fully working (no critical warnings) design. Thanks, mantoz
