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Altera_Forum
Honored Contributor
Honored ContributorStratix III dev kit: factory design doesn't meet timing requirements - why?
Hi all, some days ago we received our Stratix III DSP development kit, and now we are playing with it. In particular we started from the basic stuff, using the example which comes with the boa...
Altera_ForumHonored Contributor
Honored ContributorI have the same problem as you, I don't know how to solve those critical warnings.
If someone can help us! This topic describe a similar problem, but don't solve my problem: http://www.alteraforum.com/forum/showthread.php?t=4621&highlight=sopc+sys+clk I have set the input clock as global, but warnings are still there...
