Forum Discussion

Volodymir's avatar
Volodymir
Icon for New Contributor rankNew Contributor
4 years ago

Stratix 10 PCI Express Avalon®-MM DMA Reference Design. Interrupt generation.

Hello !
Working with a Stratix 10 board. Per AN 829: PCI Express* Avalon®-MM
DMA Reference Design built the design and uploaded it to the board. I work with Windows. I successfully run DMA Read, DMA Write. After the end of the DMA procedure, I register an MSI interrupt.
Than want to additionally register user interrupts. To do this, I use the intx_req_i input, which became available after selecting Export Interrupt conduit interface. And also tried using the rxm_irq_i[15..0] inputs. I apply a logical unit signal of a certain duration to these inputs, but I do not register an interrupt.
As I understood from the description, I must first enable interrupts by accessing the PCIe Interrupt Enable Register, which is located at 0x0050.
Please tell me how to properly translate the address from BAR in order to access this register from under windows. The map of connections and addresses is shown in the picture. Thank you. .

15 Replies

Show More
  • Volodymir's avatar
    Volodymir
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hello ! thanks for your reply !
    Your question :

    • Can I know which description and which document that you are referring at ?

    This is UG - 20033 (2019.07.18) Intel Stratix10 Avalon - MM Interface for PCI Express Solutions User Guide.

    7.2.1. PCI Express Avalon-MM Bridge Register Address Map.

    • Can you specific which BAR that you need to translate ?

    as shown in the Qsys structure (picture above), from the BAR 0 register I get access to the DMA mechanism. bar4 provides access to the internal memory. at the moment I don’t know how to access the Avalon-MM to PCIe Interrupt Enable Register via CRA

    thanks for the answer

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,

    I wish to follow up with you about this forum case.

    Hoping to hear back from you so that we can proceed for next step.

    Regards,

    Wincent_Intel


  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    Thanks for reaching, Apologize that I cannot get your question very clear.


    1. As I understood from the description, I must first enable interrupts by accessing the PCIe Interrupt Enable Register, which is located at 0x0050.
    • Can I know which description and which document that you are referring at ?
    1. Please tell me how to properly translate the address from BAR in order to access this register from under windows.
    • Can you specific which BAR that you need to translate ?


    Also, I attach with AN 829 User guide, it might contain information that needed by you.

    https://www.intel.com/content/www/us/en/docs/programmable/683554/18-0/working-with-the-reference-design.html


    Regards,

    Wincent_Intel