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Volodymir's avatar
Volodymir
Icon for New Contributor rankNew Contributor
3 years ago

Stratix 10 PCI Express Avalon®-MM DMA Reference Design. Interrupt generation.

Hello ! Working with a Stratix 10 board. Per AN 829: PCI Express* Avalon®-MM DMA Reference Design built the design and uploaded it to the board. I work with Windows. I successfully run DMA Read, DM...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Thanks for reaching, Apologize that I cannot get your question very clear.


  1. As I understood from the description, I must first enable interrupts by accessing the PCIe Interrupt Enable Register, which is located at 0x0050.
  • Can I know which description and which document that you are referring at ?
  1. Please tell me how to properly translate the address from BAR in order to access this register from under windows.
  • Can you specific which BAR that you need to translate ?


Also, I attach with AN 829 User guide, it might contain information that needed by you.

https://www.intel.com/content/www/us/en/docs/programmable/683554/18-0/working-with-the-reference-design.html


Regards,

Wincent_Intel