Forum Discussion

Volodymir's avatar
Volodymir
Icon for New Contributor rankNew Contributor
3 years ago

Stratix 10 PCI Express Avalon®-MM DMA Reference Design. Interrupt generation.

Hello ! Working with a Stratix 10 board. Per AN 829: PCI Express* Avalon®-MM DMA Reference Design built the design and uploaded it to the board. I work with Windows. I successfully run DMA Read, DM...
Volodymir's avatar
Volodymir
Icon for New Contributor rankNew Contributor
3 years ago

Hello ! thanks for your reply !
Your question :

  • Can I know which description and which document that you are referring at ?

This is UG - 20033 (2019.07.18) Intel Stratix10 Avalon - MM Interface for PCI Express Solutions User Guide.

7.2.1. PCI Express Avalon-MM Bridge Register Address Map.

  • Can you specific which BAR that you need to translate ?

as shown in the Qsys structure (picture above), from the BAR 0 register I get access to the DMA mechanism. bar4 provides access to the internal memory. at the moment I don’t know how to access the Avalon-MM to PCIe Interrupt Enable Register via CRA

thanks for the answer