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Occasional ContributorStratix 10 PAC HSSI example
I'm trying to understand how to use the hssi interface in stratix 10 PAC. I had some problem on rx_data_valid (PCS Direct on serial loopback)
But unable to reproduce the issue, so i'm creating a new issue to ask how to use it properly.
I tried modifying the hssi_prbs example code, to be more precise i'm trying to change the pattern_gen.v and pattern_ver_pipelined.v into just a simple counter.
However, after changing both of them, the rx_ready is always fluctuating, and never stable at 0xff.
So, i'm at loss on how to actually use this hssi interface. I tried looking into the transceiver user guide but still don't understand how to use it. Can someone please advise me how to use the interface correctly?
here are the modifications to pattern_gen.v and pattern_ver_pipelined.v
// pattern_gen.v `timescale 1ps/1ps module pattern_gen #( parameter MAX = 'hffff, //width parameter width = 16, //width parameter low_freq_len = 8, // (width/(low_freq_len*2)) must be a whole number parameter pattern = "prbs7", // prbs7, prbs9, prbs15, prbs23, prbs31 parameter prbs_initial_value = 97 ) ( input wire clk, input wire reset, input wire enable, output wire [width-1:0] data_out, output wire valid ); reg [width-1:0] counter; always @(posedge clk) begin if (reset) counter <= 'd0; else if (enable) counter <= (counter == MAX) ? counter : counter + 'd1; else counter <= counter; end assign valid = enable & ~(counter == MAX); assign data_out = valid ? counter : 'h0; endmodule
// pattern_ver_pipelined.v `timescale 1ps/1ps module pattern_ver_pipelined #( parameter MAX = 'hffff, //width parameter width = 16, // width parameter pattern = "prbs7", // prbs7, prbs9, prbs15, prbs23, prbs31 parameter prbs_initial_value = 97 ) ( input clk, input reset, input enable, input [width-1:0] data_in, output data_locked, output reg error ); reg [width-1:0] ref_value; always @(posedge clk) begin if (reset) ref_value <= 'd0; else if (enable) ref_value <= (ref_value == MAX) ? ref_value : ref_value + 'd1; else ref_value <= ref_value; end reg [width-1:0] err_count; always @(posedge clk) begin if (reset) err_count <= 'd0; else if (enable && (ref_value == data_in)) err_count <= err_count + 'd1; else err_count <= err_count; end always @(posedge clk) begin if (reset) error <= 'd0; else if (data_locked) error <= err_count > 'd0; else error <= error; end assign data_locked = ref_value == MAX; endmodule
16 Replies
JohnT_AlteraRegular Contributor
Hi,
I would recommend you to get the design example from Algo Logic (https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/intel-fpga-pac-d5005/algo-logic-ip.html) which will consist of the MAC block where it will help you on sending and receiving the data correctly.
yashaelHi, I tried implementing a word aligner by sending a pattern (0xF0000000). because of the bitslip, the RX then will receive a different value (e.g 0x003c0000).
But then it turns out that the bitslip is not constant throughout the transfer.
To prove that there's are bitslips happening, I took a screenshot of the receiving part. This time, the prbs_din is sync using resync.
The expected sequence of the 5 first word are: 0x55555555, 0x5fffffff, 0x2a000000, 0x17a00000, 0x0aaa0000.
But if you see the screenshot, you can see that the words are getting mixed, for example
0xfd555555 is parts of the first and second correct sequence. thus showing a bit slip.Although the prbs check is shows no error, the data itself is not correct.
To reproduce this error, you can compile hssi_prbs example with the attached prbs_top.v and hssi.stp within src.zip.
Is there any pattern to this bitslip? How do I fix this bitslips?
I really need this to work, my goal is just simply moving data from 1 fpga to another.Please advise a way to correct the received data.
- yashael
Hi,
I'm extracting simulation files from Stratix 10 Native PHY IP, then simulate it in modelsim.
In the simulation, i tried using resync block for the receiver data, and some data is missing.
- JohnT_Altera
Hi,
There is no simulation for the HSSI IP. I would recommend that you try to look at the resync block which help to syncronize the data between the TX and RX before you are able to expect the correct data.
- yashael
Hello,
I tried simulating (in ModelSim 10.6d) using the native PHY PCS direct with the same parameter as in ug-20211 and the same prbs_top, prbs_gen, prbs_ver_pipelined from the hssi_prbs example.I tried simulating the same steps as in hssi_prbs.c (reset, serial loopback, and unpause tx & rx). But in the simulator itself, the data received is not the same. (comparing prbs_din with prbs_dout). Is there any special instructions or configurations or technique that I need to implement in order to use PCS direct? Can someone help me with this?
- JohnT_Altera
Hi,
May I know if you have make sure that your data is check before you locked the data?
From the rtl you provided, you are only locking the data once the counter hit MAX.
assign data_locked = ref_value == MAX;
- yashael
In the rtl I provided, I was not sure what the data_locked is used for, and its function is not clear in the example.
However, in the screenshot I sent you I used the example design (prbs pattern_generator) and not my own pattern generator (counter).
In the rx_pattern_ver waveform, we can see that the data is check before the data locked, (the pause_chk is low and the data_locked is still lo). But, even there the rx_data is not equal to tx_data.
- yashael
I compared the data in tx_parallel_data[0..31] with rx_parallel_data[0..31]. To make it clear, I attached the screenshot of logic analyzer showing the difference in tx_parallel_data and rx_parallel_data.
- JohnT_Altera
Hi,
May I know how do you compare the data? Have you make sure that your data is align when you are comparing?
- yashael
Yes I can confirm that those signal is asserted if given enough time. But why is the data on the receiving end differs from the transmitter? I observed a kind of shifted value on the receiving end. Do I have to implement an error correction module?
- JohnT_Altera
HI,
After further investigation, the TX_READY and RX_READY will not have anything to with the PRBS module. The TX_READY and RX_READY will be related to the interface readiness. Have you check if this issue is not happening on the original design?
