New ContributorStratix 10 MX HBM2 Addressing with Avalon-MM user side interface
Hello,
I am currently trying to create a design that uses the HBM2 Avalon-MM user-side interface.
I have started with this Intel Forum design, which has worked and has been quite helpful.
However, when I am trying to adapt the design to my needs, I am faced with a few confusions.
In particular, I am using a msGDMA and a write master to convert an Avalon stream to an Avalon MM format. The write DMA master is interfaced with the HBM2. I have done something similar and instantiated a read DMA master, interfaced to the same channel (and pseudo-channel) of the HBM2.
I am monitoring the read and writes of the DMAs on SignalTap. My writes seem to work perfectly. And at a given incrementing address, 256-bit writes are captured by the HBM2.
Once this is complete, the read master is triggered. Unfortunately, the read master doesn't show the data that I would expect. Writing a fixed pattern on addresses 0x0-0xFFF would only yield some of the reads to have the same constant pattern, while other reads have some erroneous bits.
My question is that if I was to write on address 0 a particular 256-bit word, why is that when I am reading address 0, not all the 256 bits are as expected?
Is there something I am overlooking with regards to addressing in the HBM2? The documentation currently has very limited support for Avalon MM use cases.
Another puzzling thing is that when I connect a write DMA to one pseduo-channel and the read DMA to another pseduo-channel of the same HBM2 channel, I get completely different reads from what I had written? Is this expected behavior? Can one not access the memory of the same channel via either of the pseduo-channels?
Thank you for the help
