Stratix 10 MX HBM2 Addressing with Avalon-MM user side interface

Hello Adzim,

Thank you for directing me to the KDB.

Unfortunately, I have migrated my design to Quartus 21.1 but the problem still persists.

i.e. when both read and write Avalon masters are connected to the HBM2, reads are not as expected when reading a particular address. A few bits are always incorrect in consecutive reads.

Furthermore, when the two Avalon masters are connected to different pseuo-channels (of the same channel) of the HBM2, the reads are completely different.

Would appreciate it if you could verify if this is expected behavior.

Thank you.