Hello, I have been trying to get an MCDMA example design working on a Stratix 10 MX device (1SM21BEU2F55E2VG). You can consider me a beginner with the Intel FPGAs. The project details are a...
Thank you for your reply. I am providing the information below that you have requested for. I have also attached the screenshots of relevant configuration/outputs that could provide more insight into the issue.
I am using "H-Tile Multichannel DMA Intel FPGA IP for PCI Express" on Stratix 10 MX device (1SM21BEU2F55E2VG). I generated the example design simply by clicking on the "Generate Example Design" button, which generated the Quartus project files (named pcie_ed.qar) and the software codes containing the kernel and user codes. You can find all IP configuration details in the screenshots.
SRIOV was disabled. I wanted to have a bare minimum working MCDMA - AVMM design.
I understand. In this case, I was using the kernel+user code that was generated along with the Quartus example design files (present in the software directory).
I followed this for the BIOS configuration + setting up hugepages + loading uio + compiling and loading ifc_uio driver process, and I did not see any error here.
For the tests, I started with the devmem utility and simple_app examples. I have attached the screenshots. However, not much debug info/error info is available, and there is nothing in the kernel log too. Same goes for the examples too.
I noticed that, but chose to continue despite that. The server supports PCIe Gen3 (and Gen4 too), and the link configuration is set to automatic. If needed, I can fix that to Gen3; let me know.
Let me know if you need any further information in this regard. Thanks!
Besides, for the devmem utility, are you trying to perform the IP reset as in the Step 4. of Section 3.5.2.3.3.? The command you entered seems different from the one specified in the IP reset step.
It is suggested to change the host PCIe support to Gen3 which follows the design. Could you try to perform the tests again after the changes made?