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GMcCa2's avatar
GMcCa2
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3 years ago
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Stratix 10 LVDS SERDES fitter error 14566

I'm trying to compile a design with 2 Tx LVDS SERDES that both cover multiple banks. I'm compiling for the 1SX210HN3F43I3VG (Quartus project archive attached).

For the first SERDES I have the pins assigned to banks 3J, 3K and 3L, with the reference clock for the PLL assigned to a CLK pin on bank 3K. For the other SERDES I have the pins assigned to banks 3B, 3C and 3D, with the reference clock for the PLL assigned to a CLK pin on bank 3C.

From the documentation, the PLL should be able to drive the Tx SERDES in the adjacent banks. (https://www.intel.com/content/www/us/en/docs/programmable/683792/22-1-20-0-1/plls-driving-differenti...)

But I get the following errors during fit (same error for both channels):

Error(14566): The Fitter cannot place 2 periphery component(s) due to conflicts with existing constraints (2 LVDS_CHANNEL(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

If I remove all my pin assignments, the compiler picks pins on the same banks and it has no errors, but when I specify the exact pins I want on those banks that are better for board layout, then it doesn't work. Is there restrictions to which pins on adjacent bank the PLL can drive the SERDES?

I had a previous iteration of the design compile with the pinout I would like to use, but it was on an older version of Quartus (21.2 I believe it was). That design's IP was setup with an external PLL block at that point, so maybe I've configured something incorrectly in the latest design, but I can't seem to figure out what that could be.

  • GMcCa2's avatar
    GMcCa2
    3 years ago

    I manage to get it to compile with the pinout I would like. Here's what I had to do:

    I have a SERDES IP with 52 Tx channels. For the 3A/3B/3C setup (PLL reference on 3B) I originally had them split like so:

    • 3A: tx_data[0..15]
    • 3B: tx_data[16..38]
    • 3C: tx_data[39..51]

    When I re-arrange the data map to the SERDES IP to this:

    • 3A: tx_data[23..38]
    • 3B: tx_data[0..22]
    • 3C: tx_data[39..51]

    Then it compiles with no errors. (I also re-arranged the input data to the IP in the same way so that it is functionally equivalent.)

    So it looks like the fitter doesn't like it when the channels that are on the same bank as the PLL aren't the first one mapped to SERDES IP block. Seems like a bug to me, so a fix would be nice, but a note in the documentation would probably do the trick.

7 Replies

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,


    Let me replicate your design first and see what I can do to help you solve the issue. I will keep you updated.


    Regards,

    Aqid


    • GMcCa2's avatar
      GMcCa2
      Icon for New Contributor rankNew Contributor
      3 years ago

      Using Quartus 22.3.0 (on Windows 10).

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,


    Thank you for the confirmation.

    I have checked the user guide, it said that if you use the dedicated reference clock input of a PLL in one bank to clock multiple PLLs that drive the LVDS channels in other banks, you must manually promote the reference clock to the global clock network and ensure timing closure.


    Could you try this first and report back to us?


    Regards,

    Aqid


    • GMcCa2's avatar
      GMcCa2
      Icon for New Contributor rankNew Contributor
      3 years ago

      Yes, I've also seen that note, from 3.1.6 of SERDES user guide which says:

      Each I/O bank contains its own PLL. The I/O bank PLL can drive all receiver and transmitter channels in the same bank, and transmitter channels in adjacent I/O banks. However, the I/O bank PLL cannot drive receiver channels in another I/O bank or transmitter channels in non-adjacent I/O banks.

      Each PLL has its own dedicated reference clock input. You can use the dedicated reference clock input of a PLL in one bank to clock multiple PLLs that drive the LVDS channels in other banks. For example, you can use the dedicated reference clock input of bank 2A to clock the PLLs in banks 2B and 2C. If you share the reference clock source this way, you must manually promote the reference clock to the global clock network and ensure timing closure.

      I am doing transmitter channels, so my design uses one PLL to drive the channels in the same bank and the adjacent banks (Figure 17 from 3.1.6.1, not Figure 18). I do not want to split the reference clock to multiple PLLs, as this will require the PLL to be reference from the global clock network, which will decrease it's performance, and as noted will require me to ensure timing closure.

      Even though it is meant for multiple PLLs, I did try promoting the reference clock to the global clock network at some point to see what would happen and it did not fix the error.

      The main issue I have with this error is that if I remove all my pin assignments then the compiler is able to place the design with no errors. It even places them in the same banks that I would like to use (3B/3C/3D and 3J/3K/3L). This means that it is able to place the PLL in one bank and drive SERDES in the adjacent banks without issue. It only errors when I specify which pins in those banks I would like to use. The documentation says the PLL can drive all the SERDES transmitter channels in the adjacent banks, not some of them. Either there is an issue with the fitter or with the documentation.

  • GMcCa2's avatar
    GMcCa2
    Icon for New Contributor rankNew Contributor
    3 years ago

    I manage to get it to compile with the pinout I would like. Here's what I had to do:

    I have a SERDES IP with 52 Tx channels. For the 3A/3B/3C setup (PLL reference on 3B) I originally had them split like so:

    • 3A: tx_data[0..15]
    • 3B: tx_data[16..38]
    • 3C: tx_data[39..51]

    When I re-arrange the data map to the SERDES IP to this:

    • 3A: tx_data[23..38]
    • 3B: tx_data[0..22]
    • 3C: tx_data[39..51]

    Then it compiles with no errors. (I also re-arranged the input data to the IP in the same way so that it is functionally equivalent.)

    So it looks like the fitter doesn't like it when the channels that are on the same bank as the PLL aren't the first one mapped to SERDES IP block. Seems like a bug to me, so a fix would be nice, but a note in the documentation would probably do the trick.

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hello,


    Thank you for pointing out this for the benefit of the community.

    I will redirect this issue to the internal team to either fix it if it is a bug or update the documentation to avoid any confusion in future.

    We do regret the inconvenience caused.


    If you have a new question regarding this, please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.


    Regards,

    Aqid