Stratix 10 LVDS SERDES fitter error 14566

I manage to get it to compile with the pinout I would like. Here's what I had to do:

I have a SERDES IP with 52 Tx channels. For the 3A/3B/3C setup (PLL reference on 3B) I originally had them split like so:

• 3A: tx_data[0..15]
• 3B: tx_data[16..38]
• 3C: tx_data[39..51]

When I re-arrange the data map to the SERDES IP to this:

• 3A: tx_data[23..38]
• 3B: tx_data[0..22]
• 3C: tx_data[39..51]

Then it compiles with no errors. (I also re-arranged the input data to the IP in the same way so that it is functionally equivalent.)

So it looks like the fitter doesn't like it when the channels that are on the same bank as the PLL aren't the first one mapped to SERDES IP block. Seems like a bug to me, so a fix would be nice, but a note in the documentation would probably do the trick.